1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a self-aligning polysilicon gate in the fabrication of integrated circuits.
2 Description of the Prior Art
In the manufacture of integrated circuits, it is a conventional process to use a polysilicon gate as a self-aligning mask for a source/drain ion implantation. This single layer polysilicon gate of the prior art, with or without an upper polycide layer, is not suitable for high energy implantation; that is, above about 100 Kev for boron, for example. As shown in FIG. 1A, the grain boundaries 6 of polysilicon gate 5 act as a channel for the implanted ions 15 to penetrate through the gate 5 and gate silicon oxide 11 and into the substrate 10 beneath the gate 5. The ions should appear only in the unmasked regions 16, but they also appear in the masked region 17 because of the ineffectiveness of the mask.
The present invention uses a multilayer polysilicon gate, with or without an upper polycide layer, as the mask for source/drain ion implantation. As seen in FIG. 1B, the grain boundaries 8 of the polysilicon gate 7 are misaligned and therefore, do not allow the passage of ions through the gate 7. The implanted ions appear only in the unmasked regions 16.
A multilayer concept has been used in a number of patents, although the layers are composed of different materials and/or they are used for different purposes than that of the present invention. U.S. Pat. No. 4,816,425 to McPherson describes a process in which a thin layer of silicon oxide is formed overlying a layer of polysilicon in order to enhance the adhesion of a sputtered metal silicide to the polysilicon. U.S. Pat. No. 4,923,526 to Harada et al describes a process for forming multiple metal layers with intervening layers formed of a compound of the metal and a reactive gas. These layers serve to suppress the growth of grains in the metal layers and to suppress electromigration of grain boundaries. U.S. Pat. Nos. 4,829,024 to Klein et al, 4,354,309 to Gardiner et al, and 5,093,700 to Sakata describe multiple polysilicon layers used to limit grain size. U.S. Pat. No. 4,329,706 to Crowder et al details an improved interconnection for integrated circuits using layers of polysilicon and metal silicide. Co-pending U.S. patent application Ser. No. 08/005,079 filed on Jan. 15, 1993 by Heng Sheng Huang describes a process using multiple polysilicon and native silicon oxide layers to solve the problem of native silicon oxide islands remaining within the polysilicon and buried contact to source/drain or emitter region interface.